1. Technical Field
The present invention relates to routing signals through a probe card of a test system used to test integrated circuits (ICs) on a wafer.
2. Related Art
A test system controller with increased test channels is a significant cost factor for a test system, as is a probe card with components to routing lines to accommodate a limited number of test system channels. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel. Unfortunately, wafer size has typically outpaced the development of test system controllers, so available channels are typically inadequate for testing all Devices Under Test (DUTs) on a wafer at the same time. It is, thus, desirable to provide a probe card that allows increased test flexibility.
One conventional way to accommodate efficient testing of components on a wafer with a limited number of test channels, is to switch the test channels between different probe contacts on the probe card. Schemes used by probe card manufacturers for switching channels on a probe card include relays, analog switches and jumpers. One scheme that includes switches in a test system is described in U.S. Pat. No. 5,736,850 entitled “Configurable Probe Card For Automatic Test Equipment,” by Dennis Legal, assigned to Teradyne, Inc. The benefit of switching channel paths is illustrated by FIGS. 1A–1B. In FIGS. 1A–1B, testing of a wafer is performed by moving a probe card 1 over four different quadrants of a wafer 2, two quadrants being shown. As illustrated in FIG. 1A, only a portion of the probe contacts 3 of the probe card 1 are over the wafer enabling testing. Hence, switching is used to reroute channels from the test probes not over the wafer to test probes over the wafer in the probe card 1 to accommodate testing in quadrants as shown. As shown in FIG. 1B, probe contacts that were over the wafer in FIG. 1A are no longer over the wafer, while some contacts not over the wafer in FIG. 1A have now been moved over the wafer in FIG. 1B. Thus, switching again can be performed between the step shown in FIG. 1A and the step of FIG. 1B to connect test system channels to test probes provided over the wafer. Drawbacks to conventional switching schemes on probe cards include: relays being notoriously unreliable, jumpers being usable only a few times before the bond pads will no longer take solder, and analog switches do not provide the signal swapping density often desired for flexibility.
Another conventional way to accommodate efficient testing of components on a wafer with a limited number of test channels, is to fan out a signal from a test system controller in the probe card to multiple transmission lines. In other words, test signals normally provided to a single DUT are fanned out to multiple DUTs in the probe card. This method can enable testing of all DUTs during a single touchdown with a limited number of test system channels, a condition suitable for bum in testing where during heating of the wafer multiple touch downs of the probe card to the wafer is sometimes impractical.
To better assure test integrity with fan out, increased circuitry is provided on the probe card to minimize the effect of a fault on one of the fan out lines. A fault (short circuit) in a component connected on a fanned out line will severely attenuate the test signal for all devices on the fanned out test system channel. U.S. Pat. No. 6,603,323 entitled “Closed-Grid Bus Architecture For Wafer Interconnect Structure,” incorporated herein by reference, describes a solution by providing isolation resistors between the channel line branch points and probes to reduce attenuation caused by the faulty component. A further solution is provided in U.S. patent application Ser. No. 10/693,133, incorporated herein by reference, entitled “Isolation Buffers With Controlled Equal Time Delays” describing a system where isolation buffers are used between channel line branch points and probes, with circuitry included to assure the isolation buffers each provide a uniform delay.
FIG. 2 shows, for reference, a conventional test system block diagram. The test system includes a test system controller 4, or general purpose computer, connected by a communication cable 6 to a test head 8. The test system further includes a prober 10 made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being movable to contact the wafer 14 with probes 16 on a probe card 18. The prober 10 includes the probe card 18 supporting probes 16 which contact DUTs formed on the wafer 14.
In the test system, test data is generated by the test system controller 4 and transmitted through the communication cable 6, test head 8, probe card 18, probes 16 and ultimately to DUTs on the wafer 14. Test results are then provided from DUTs on the wafer back through the probe card 18 to the test head 8 for transmission back to the test system controller 4. Once testing is complete, the wafer is diced up to separate the DUTs.
Test data provided from the test system controller 4 is divided into the individual test channels, provided through the cable 6 and separated in the test head 8 so that each channel is carried to a separate one of the probes 16. The channels from the test head 8 are linked by connectors 24, such as flexible cable connectors, pogo pins or ZIF connectors to the probe card 18. The probe card 18 then links each channel to a separate one of the probes 16.
FIG. 3 shows a cross sectional view of components of a typical probe card 18. The probe card 18 is configured to provide both electrical pathways and mechanical support for the spring probes 16 that will directly contact the wafer. The probe card electrical pathways are provided through a printed circuit board (PCB) 30, an interposer 32, and a space transformer 34. Test data from the test head 8 is provided through flexible cable connectors 24 typically connected around the periphery of the PCB 30. Channel transmission lines 40 distribute signals from the connectors 24 horizontally in the PCB 30 to contact pads on the PCB 30 to match the routing pitch of pads on the space transformer 34. Switching elements 25 (including relays, analog switches, or jumpers) are provided on the PCB 30 in the path of at least some channel transmission lines 40 to enable for selectively routing the channel to a number of different paths on the PCB 30. The interposer 32 includes a substrate 42 with spring probe electrical contacts 44 disposed on both sides. The interposer 32 electrically connects individual pads 31 on the PCB 30 to pads forming a land grid array (LGA) on the space transformer 34. Traces 46 in a substrate 45 of the space transformer 34 distribute or “space transform” connections from the LGA to spring probes 16 configured in an array. The space transformer substrate 45 is typically constructed from either multi-layered ceramic or organic based laminates. The space transformer substrate 45 with embedded circuitry, probes and LGA is referred to as a probe head.
Mechanical support for the electrical components is provided by a back plate 50, bracket (Probe Head Bracket) 52, frame (Probe Head Stiffener Frame) 54, leaf springs 56, and leveling pins 62. The back plate 50 is provided on one side of the PCB 30, while the bracket 52 is provided on the other side and attached by screws 59. The leaf springs 56 are attached by screws 58 to the bracket 52. The leaf springs 56 extend to movably hold the frame 54 within the interior walls of the bracket 52. The frame 54 then includes horizontal extensions 60 for supporting the space transformer 34 within its interior walls. The frame 54 surrounds the probe head and maintains a close tolerance to the bracket 52 such that lateral motion is limited.
Leveling pins 62 complete the mechanical support for the electrical elements and provide for leveling of the space transformer 34. The leveling pins 62 are adjusted so that brass spheres 66 provide a point contact with the space transformer 34. The spheres 66 contact outside the periphery of the LGA of the space transformer 34 to maintain isolation from electrical components. Leveling of the substrate is accomplished by precise adjustment of these spheres through the use of advancing screws, or leveling pins 62. The leveling pins 62 are screwed through supports 65 in the back plate 50 and PCB 30. Motion of the leveling pin screws 62 is opposed by leaf springs 56 so that spheres 66 are kept in contact with the space transformer 34.
FIG. 4 shows an exploded assembly view of components of the probe card of FIG. 3. FIG. 4 shows attachment of the back plate 50, PCB 30, and bracket 52 using two screws 59. Four leveling screws 62, are provided through the back plate 50 and PCB 30 to contact four spheres 66 near the corners of the space transformer substrate 34. The frame 54 is provided directly over the space transformer substrate 34, the frame 54 fitting inside the bracket 52. The leaf springs 56 are attached by screws 58 to the bracket 52. Two screws 58 are shown for reference, although additional screws 58 (not shown) are provided around the entire periphery to attach the leaf springs.
FIG. 5 shows a perspective view of the opposing side of PCB 30 illustrating the arrangement of connectors 24 and switches 25 formed around the periphery of PCB 30. In FIG. 5, the connectors 24 and switches 25 of the PCB 30 are facing down and not shown. In typical probe cards, the connectors 24 are located around the periphery of the probe card, and are configured to mate with connectors that are typically arranged in a similar fashion on the test head. The switches 25 are typically large components with a limited number of switching elements that occupy a considerable amount of space. The switches 25 are provided between the connectors 24 and pads on the opposing side of PCB 30. The switches 25 are provided in spacing available if such spacing exists between the probe card and test head.